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| 3 july 2013 docid024849 rev 1 1/89 stm32f030x4 stm32f030x6 stm32f030x8 value-line arm-based 32-bit mcu with 16 to 64-kb flash, timers, adc, communication interfaces, 2.4-3.6 v operation datasheet ?? target specification features ? core: arm ? 32-bit cortex?-m0 cpu, frequency up to 48 mhz ? memories ? 16 to 64 kbytes of flash memory ? 4 to 8 kbytes of sram with hw parity checking ? crc calculation unit ? reset and power management ? voltage range: 2.4 v to 3.6 v ? power-on/power down reset (por/pdr) ? low power modes: sleep, stop, standby ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? up to 55 fast i/os ? all mappable on external interrupt vectors ? up to 36 i/os with 5 v tolerant capability ? 5-channel dma controller ? 1 x 12-bit, 1.0 s adc (up to 16 channels) ? conversion range: 0 to 3.6 v ? separate analog supply from 2.4 up to 3.6 v ? up to 10 timers ? one 16-bit 7-channel advanced-control timer for 6 channels pwm output, with deadtime generation and emergency stop ? one 16-bit timer, with up to 4 ic/oc, usable for ir control decoding ? one 16-bit timer, with 2 ic/oc, 1 ocn, deadtime generation and emergency stop ? two 16-bit timers, each with ic/oc and ocn, deadtime generation, emergency stop and modulator ga te for ir control ? one 16-bit timer with 1 ic/oc ? one 16-bit basic timer ? independent and system watchdog timers ? systick timer: 24-bit downcounter ? calendar rtc with alarm and periodic wakeup from stop/standby ? communication interfaces ? up to two i 2 c interfaces: one supporting fast mode plus (1 mbit/s) with 20 ma current sink ? up to two usarts supporting master synchronous spi and modem control; one with auto baud rate detection ? up to two spis (18 mbit/s) with 4 to 16 programmable bit frame ? serial wire debug (swd) table 1. device summary reference part number stm32f030x4 stm32f030f4 stm32f030x6 STM32F030C6, stm32f030k6 stm32f030x8 stm32f030c8, stm32f030r8 lqfp48 7x7 mm lqfp64 10x10 mm lqfp32 7x7 mm tssop20 www.st.com http:///
contents stm32f030x4 stm32f030x6 stm32f030x8 2/89 docid024849 rev 1 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm? cortextm-m0 core with embedded flash and sram . . . . . . . . . 12 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 13 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 16 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11.2 general-purpose timers (tim3, tim14..17) . . . . . . . . . . . . . . . . . . . . . . 19 3.11.3 basic timer tim6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11.5 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 universal synchronous/asynchronous re ceiver transmitters (usart) . . 22 http:/// docid024849 rev 1 3/89 stm32f030x4 stm32f030x6 stm32f030x8 contents 4 3.15 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 41 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 41 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.17 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.18 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.19 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 http:/// contents stm32f030x4 stm32f030x6 stm32f030x8 4/89 docid024849 rev 1 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 84 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 http:/// docid024849 rev 1 5/89 stm32f030x4 stm32f030x6 stm32f030x8 list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f030x device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. stm32f030x i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8. stm32f030x usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9. stm32f030x spi implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. alternate functions selected through gpioa_af r registers for port a . . . . . . . . . . . . . . . 31 table 13. alternate functions selected through gpiob_af r registers for port b . . . . . . . . . . . . . . . 32 table 14. stm32f030x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 19. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 22. typical and maximum current consumption from v dd supply at vdd = 3.6 . . . . . . . . . . . 43 table 23. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 43 table 24. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 44 table 25. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 44 table 26. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 27. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 30. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 31. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 32. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 33. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 34. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 35. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 36. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 37. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 38. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 39. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 40. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 41. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 42. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 43. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 44. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 45. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 46. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 47. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 http:/// list of tables stm32f030x4 stm32f030x6 stm32f030x8 6/89 docid024849 rev 1 table 48. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 49. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 50. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 51. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 52. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 53. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 54. wwdg min-max timeout value @48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 55. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 56. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 57. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 58. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . . 76 table 59. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 78 table 60. lqfp32 ? 7 x 7mm 32-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 80 table 61. tssop20 ? 20-pin thin shrink small outline pa ckage mechanical data . . . . . . . . . . . . . . . 82 table 62. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 63. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 64. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 http:/// docid024849 rev 1 7/89 stm32f030x4 stm32f030x6 stm32f030x8 list of figures 7 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. lqfp64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. lqfp48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. lqfp32 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. tssop20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7. stm32f030x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 12. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 13. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 15. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 16. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 17. five volt tolerant (ft and ftf) i/o input characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 18. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 19. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 20. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 21. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 22. i 2 c bus ac waveforms and measurement ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 23. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 24. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 25. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 26. lqfp64 ? 10 x 10 mm 64 pin low-profile quad fl at package outline . . . . . . . . . . . . . . . . . 76 figure 27. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 28. lqfp48 ? 7 x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 78 figure 29. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 30. lqfp32 ? 7 x 7mm 32-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 80 figure 31. lqfp32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 32. tssop20 - 20-pin thin shrink sm all outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 33. tssop20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 figure 34. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 http:/// introduction stm32f030x4 stm32f030x6 stm32f030x8 8/89 docid024849 rev 1 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f030x microcontrollers. this stm32f030x4, stm32f030x6, and stm32f030x8 datasheet should be read in conjunction with the stm32f0xxxx reference m anual (rm0091). the reference manual is available from the stmicroelectronics website www.st.com. for information on the arm cortex?-m0 core, please refer to the cortex?-m0 technical reference manual, available from the www. arm.com website at the following address: http://infocenter.arm.com/help/index.jsp? topic=/com.arm.doc.ddi0432c/index.html. http:/// docid024849 rev 1 9/89 stm32f030x4 stm32f030x6 stm32f030x8 description 11 2 description the stm32f030x microcontroller incorporates the high-performance arm cortex?-m0 32- bit risc core operating at a 48 mhz frequ ency, high-speed embedded memories (up to 64 kbytes of flash memory and up to 8 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (up to two i 2 cs, up to two spis, and up to two usarts), one 12-bit adc, up to 6 general-purpose 16-bit timers and an advanced-control pwm timer. the stm32f030x microcontroller operates in t he -40 to +85 c temperature range, from a 2.4 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f030x microcontroller includes devices in four different packages ranging from 20 pins to 64 pins. depending on the device chosen, different sets of peripherals are included. the description below provides an overview of the complete range of stm32f030x peripherals proposed. these features make the stm32f030x microc ontroller suitable for a wide range of applications such as applic ation control and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming platforms, e-bikes, consumer appliances, printers, scanners, alarm system s, video intercoms, and hvacs. http:/// description stm32f030x4 stm32f030x6 stm32f030x8 10/89 docid024849 rev 1 table 2. stm32f030x device features and peripheral counts peripheral stm32f030f4 stm32f030k6 STM32F030C6/c8 stm32f030r8 flash (kbytes) 16 32 32 64 64 sram (kbytes) 4 4 4 8 8 timers advanced control 1 (16-bit) general purpose 4 (16-bit) (1) 4 (16-bit) (1) 4 (16-bit) (1) 5 (16-bit) 5 (16-bit) basic - - - 1 (16-bit) 1 (16-bit) comm. interfaces spi 1 (2) 1 (2) 1 (2) 22 i 2 c1 (3) 1 (3) 1 (3) 22 usart 1 (4) 1 (4) 1 (4) 22 12-bit synchronized adc (number of channels) 1 (11 channels) 1 (12 channels) 1 (12 channels) 1 (18 channels) gpios 15 26 39 55 max. cpu frequency 48 mhz operating voltage 2.4 to 3.6 v operating temperature ambient operating temperature: -40 c to 85 c packages tssop20 lqfp32 lqfp48 lqfp64 1. tim15 is not present. 2. spi2 is not present. 3. i2c2 is not present. 4. usart2 is not present. http:/// docid024849 rev 1 11/89 stm32f030x4 stm32f030x6 stm32f030x8 description 11 figure 1. block diagram 1. timer6, timer15, spi2, usart2 and i2c2 are available on st m32f030x8 devices only. msv32137v1 4 channels 3 compl. channels brk, etr input as af 4 ch., etr as af 1 channel as af 2 channels 1 compl, brk as af 1 channel 1 compl, brk as af 1 channel 1 compl, brk as af ir_out as af rx, tx,cts, rts, ck as af rx, tx,cts, rts, ck as af scl, sda, smba (20 ma for fm+) as af scl, sda as af @ v dd @ v dda ahbpclk apbpclk adcclk usartclk hclk fclk pa[15:0] pb[15:0] pc[15:0] pd2 pf[1:0] pf[7:4] @ v dda 55 af mosi, miso, sck, nss as af v dda v ssa gp dma 5 channels cortex-m0 cpu f hclk = 48 mhz serial wire debug nvic gpio port a gpio port b gpio port c gpio port d gpio port f ext. it wkup spi1 spi2 syscfg if timer 6 dbgmcu wwdg apb ahb crc reset & clock control timer 1 timer 3 timer 14 timer 15 timer 16 timer 17 usart1 usart2 i2c 1 i2c2 power controller xtal osc 4-32 mhz iwdg supply supervision por/pdr power volt.reg 3.3 v to 1.8 v rc hs 14 mhz rc hs 8 mhz rc ls pll flash interface flash up to 64 kb, 32 bits obl sram 4 / 8 kb temp. sensor if 12-bit adc1 swclk swdio as af mosi/miso, sck/nss, as af 16 ad inputs bus matrix @ v dda @ v dd v dd18 por reset int v dd = 2.4 to 3.6 v v ss nrst v dda v dd osc_in (pf0) osc_out (pf1) osc32_in (pc14) osc32_out (pc15) tamper-rtc (alarm out) rtc rtc interface xtal32 khz @ vdd sram controller ahb decoder http:/// functional overview stm32f030x4 stm32f030x6 stm32f030x8 12/89 docid024849 rev 1 3 functional overview 3.1 arm ? cortex tm -m0 core with embe dded flash and sram the arm cortex?-m0 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f0xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: ? up to 8 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail- critical applications. ? the non-volatile memory is divided into two arrays: ? 16 to 64 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, th e flash memory cannot be read from or written to if either debug features ar e connected or boot in ram is selected ? level 2: chip readout protection, debug fe atures (cortex-m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector op tion bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10. http:/// docid024849 rev 1 13/89 stm32f030x4 stm32f030x6 stm32f030x8 functional overview 22 3.4 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a crc-32 (ethernet) polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = 2.4 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v dda = 2.4 to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll. the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. for more details on how to connect power pins, refer to figure 10: power supply scheme . 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . 3.5.3 voltage regulator the regulator has three operating modes: main (mr), low power (lpr) and power down. ? mr is used in normal operating mode (run) ? lpr can be used in stop mode where the power demand is reduced ? power down is used in standby mode: the re gulator output is in high impedance: the kernel circuitry is powered do wn, inducing zero consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. http:/// functional overview stm32f030x4 stm32f030x6 stm32f030x8 14/89 docid024849 rev 1 3.5.4 low-power modes the stm32f030x microcontroller supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the volt age regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 ex ternal lines or the rtc alarm. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for the standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 3.6 clocks and startup system clock selection is perf ormed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resona tor or oscillator). several prescalers allow the ap plication to configure the fr equency of the ahb and the apb domains. the maximum freq uency of the ahb and t he apb domains is 48 mhz. http:/// docid024849 rev 1 15/89 stm32f030x4 stm32f030x6 stm32f030x8 functional overview 22 figure 2. clock tree 1. lsi/lse is not available on stm32f030x8 devices. /32 4-32 mhz hse osc osc_in osc_out osc32_in osc32_out 8 mhz hsi rc to iwdg pll x2,x3,.. x16 pllmul mco main clock output ahb /2 pllclk hsi hse apb prescaler /1,2,4,8,16 adc prescaler /2,4 hclk pllclk to ahb bus, core, memory and dma to adc 14 mhz max lse lsi hsi hsi hse to rtc pllsrc sw mco /8 sysclk rtcclk rtcsel[1:0] sysclk to tim1,3,6, 14,15,16,17 if (apb1 prescaler =1) x1 else x2 flitfclk to flash programming interface hsi14 14 mhz hsi14 rc hsi14 /244 lse to i2c1 to usart1 lse hsi sysclk /2 pclk sysclk hsi pclk ms32138v1 to cortex system timer fhclk cortex free running clock to apb peripherals ahb prescaler /1,2,..512 css /1,2, 3,..16 lse osc 32.768khz lsi rc 40khz lsi lse (1) (1) http:/// functional overview stm32f030x4 stm32f030x6 stm32f030x8 16/89 docid024849 rev 1 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.8 direct memory a ccess controller (dma) the 5-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardw are dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i2c, usart, all timx timers (except tim14) and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m0) and 4 priority levels. ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 24 edge detector lines used to generate interrupt/event requ ests and wake-up the system. ea ch line can be independently configured to select the trig ger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains t he status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 55 gpios can be connected to the 16 external interrupt lines. http:/// docid024849 rev 1 17/89 stm32f030x4 stm32f030x6 stm32f030x8 functional overview 22 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and 2 internal (temperature sensor/voltage reference measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conv ersion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in 17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 4. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb http:/// functional overview stm32f030x4 stm32f030x6 stm32f030x8 18/89 docid024849 rev 1 3.11 timers and watchdogs devices of the stm32f0xx family include up to six general-purpose timers, one basic timer and an advanced control timer. table 5 compares the features of the advanced-c ontrol, general-purpose and basic timers. 3.11.1 advanced-c ontrol timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on 6 channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can t herefore work together with the other timers via the timer link feature for sy nchronization or event chaining. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general purpose tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim14 16-bit up any integer between 1 and 65536 no 1 no tim15 (1) 16-bit up any integer between 1 and 65536 yes 2 yes tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 yes basic tim6 (1) 16-bit up any integer between 1 and 65536 yes 0 no 1. available on stm32f030x8 devices only. http:/// docid024849 rev 1 19/89 stm32f030x4 stm32f030x6 stm32f030x8 functional overview 22 3.11.2 general-purpose ti mers (tim3, tim14..17) there are five synchronizable general-purpose timers embedded in the stm32f030x devices (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim3 stm32f030x devices feature a synchronizable 4-channel general-purpose timer based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. tim3 features 4 independent channels for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim3 general-purpose timer can work wi th the tim1 advanced-control timer via the timer link feature for synchronization or event chaining. it provides independent dma request generation. the tim3 timer is capable of handling quadr ature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. its counter can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-re load upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim15, tim16 and tim17 these timers are based on a 16-bit auto-r eload upcounter and a 16-bit prescaler. tim15 has two independent channels, wher eas tim16 and tim17 feature one single channel for input capture/output compare, pwm or one-pulse mode output. the tim15, tim16 and tim17 timers can work together, and tim15 can also operate with tim1 via the timer link feature for synchronization or event chaining. tim15 can be synchronized with tim16 and tim17. tim15, tim16, and tim17 have a compleme ntary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.11.3 basic timer tim6 this timer is mainly used as a generic 16-bit time base. 3.11.4 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free http:/// functional overview stm32f030x4 stm32f030x6 stm32f030x8 20/89 docid024849 rev 1 running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.11.5 system win dow watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.11.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.12 real-time clock (rtc) the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month ? programmable alarm with wake up from stop and standby mode capability ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy ? 2 anti-tamper detection pins with programma ble filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? periodic wakeup from stop/standby ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32 http:/// docid024849 rev 1 21/89 stm32f030x4 stm32f030x6 stm32f030x8 functional overview 22 3.13 inter-integrated circuit interfaces (i 2 c) up to two i 2 c interfaces (i2c1 and i2c2) can operate in multimaster or slave modes. both can support standard mode (up to 100 kbit/s) or fast mode (up to 400 kbit/s). i2c1 also supports fast mode plus (up to 1 mbit/s) with 20 ma output drive. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, i2c1 provides hardware su pport for smbus 2.0 and pmbus 1.1: arp capability, host notify prot ocol, hardware crc ( pec) generation/verification, timeouts verifications and alert protocol management. the i2c interfaces can be served by the dma controller. refer to table 7 for the differences be tween i2c1 and i2c2. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 7. stm32f030x i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode xx 10-bit addressing mode xx standard mode (up to 100 kbit/s) xx fast mode (up to 400 kbit/s) xx fast mode plus with 20 ma output drive i/os (up to 1 mbit/s) x- smbus x- http:/// functional overview stm32f030x4 stm32f030x6 stm32f030x8 22/89 docid024849 rev 1 3.14 universal synchronous/asynch ronous receiver transmitters (usart) the device embeds up to two universal synchronous/asynchronous receiver transmitters (usart1 and usart2), which communicate at speeds of up to 6 mbit/s. they provide hardware management of the cts and rts signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. the usart1 supports also auto baud rate feature. the usart interfaces can be served by the dma controller. refer to table 8 for the differences between usart1 and usart2. 3.15 serial peripheral interface (spi) up to two spis are able to communicate up to 18 mbits/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. refer to table 9 for the differences between spi1 and spi2. 3.16 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. table 8. stm32f030x usart implementation usart modes/features (1) 1. x = supported. usart1 usart2 hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x x single-wire half-duplex communication x x receiver timeout interrupt x - auto baud rate detection x - table 9. stm32f030x spi implementation spi features (1) 1. x = supported. spi1 spi2 hardware crc calculation x x rx/tx fifo x x nss pulse mode x x ti mode x x http:/// docid024849 rev 1 23/89 stm32f030x4 stm32f030x6 stm32f030x8 pinouts and pin descriptions 32 4 pinouts and pin descriptions figure 3. lqfp64 64-pin package pinout 1. the above figure shows the package top view. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vdd pc14/osc32_in pf0/osc_in nrst pc0 pc1 pc2 pc3 vssa vdda pa0 pa1 pa2 vdd pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa15 pa14 pf7 pf6 pa13 pa12 pa11 pa10 pa9 pa8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa3 pf4 pa4 pa5 pa6 pa7 pc4 pc5 pb0 pb1 pb2 pb10 pb11 lqfp64 pc13 ms32729v1 pf5 vss vdd vss pf1/osc_out pc15/osc32_out http:/// pinouts and pin descriptions stm32f030x4 stm32f030x6 stm32f030x8 24/89 docid024849 rev 1 figure 4. lqfp48 48-pin package pinout 1. the above figure shows the package top view. figure 5. lqfp32 32-pin package pinout 1. the above figure shows the package top view. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 lqfp48 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb10 pb11 vss vdd pf7 pf6 pa13 pa12 pa11 pa10 pa9 pa8 pb15 pb14 pb13 pb12 vdd nrst vssa vdda pa0 pa1 pa2 vdd vss pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pa15 pa14 ms32730v1 pc13 pc14/osc32_in pf0/osc_in pf1/osc_out pc15/osc32_out ms32144v1 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 8 910111213 14 15 16 1 2 3 4 5 6 7 lqfp32 pa3 pa4 pa5 pa6 pa7 pb0 pb1 vss pa14 pa13 pa12 pa11 pa10 pa9 pa8 vdd nrst vdda pa0 pa1 pa2 vss boot0 pb7 pb6 pb5 pb4 pb3 pa15 pf0/osc_in pf1/osc_out vdd 21 http:/// docid024849 rev 1 25/89 stm32f030x4 stm32f030x6 stm32f030x8 pinouts and pin descriptions 32 figure 6. tssop20 package pinout ms32731v1 1 20 10 11 19 18 17 16 15 12 13 14 2 3 4 5 6 7 8 9 pf0/osc_in boot0 pf1/osc_out nrst vdda pa0 pa9 vdd pa14 pa6 pa7 pb1 vss pa1 pa2 pa3 pa4 pa5 pa13 pa10 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions select ed through gpiox_afr registers additional functions functions directly se lected/enabled through peripheral registers http:/// pinouts and pin descriptions stm32f030x4 stm32f030x6 stm32f030x8 26/89 docid024849 rev 1 table 11. pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions 1 1 - - vdd s complementary power supply 22 - - pc13 i/otc (1) - rtc_tamp1, rtc_ts, rtc_out, wkup2 33 - - pc14-osc32_in (pc14) i/o tc (1) - osc32_in 44 - - pc15-osc32_out (pc15) i/o tc (1) - osc32_out 5522 pf0-osc_in (pf0) i/o ft - osc_in 6633 pf1-osc_out (pf1) i/o ft - osc_out 7744 nrst i/orst device reset input / internal reset output (active low) 8 - - - pc0 i/o tta eventout adc_in10 9 - - - pc1 i/o tta eventout adc_in11 10 - - - pc2 i/o tta eventout adc_in12 11 - - - pc3 i/o tta eventout adc_in13 12 8 - - vssa s analog ground 13 9 5 5 vdda s analog power supply 14 10 6 6 pa0 i/o tta usart1_cts (2) , usart2_cts (3) adc_in0, rtc_tamp2, wkup1 15 11 7 7 pa1 i/o tta usart1_rts (2) , usart2_rts (3) , eventout adc_in1 16 12 8 8 pa2 i/o tta usart1_tx (2) , usart2_tx (3) , tim15_ch1 (3) adc_in2 17 13 9 9 pa3 i/o tta usart1_rx (2) , usart2_rx (3) , tim15_ch2 (3) adc_in3 18 - - - pf4 i/o ft eventout - 19 - - - pf5 i/o ft eventout - http:/// docid024849 rev 1 27/89 stm32f030x4 stm32f030x6 stm32f030x8 pinouts and pin descriptions 32 20 14 10 10 pa4 i/o tta spi1_nss, usart1_ck (2) usart2_ck (3) , tim14_ch1 adc_in4 21 15 11 11 pa5 i/o tta spi1_sck adc_in5 22 16 12 12 pa6 i/o tta spi1_miso, tim3_ch1, tim1_bkin, tim16_ch1, eventout adc_in6 23 17 13 13 pa7 i/o tta spi1_mosi, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, eventout adc_in7 24 - - - pc4 i/o tta eventout adc_in14 25 - - - pc5 i/o tta - adc_in15 26 18 14 - pb0 i/o tta tim3_ch3, tim1_ch2n, eventout adc_in8 27 19 15 14 pb1 i/o tta tim3_ch4, tim14_ch1, tim1_ch3n adc_in9 28 20 - - pb2 i/o ft (4) -- 29 21 - - pb10 i/o ft i2c1_scl (2) , i2c2_scl (3) - 30 22 - - pb11 i/o ft i2c1_sda (2) , i2c2_sda (3) , eventout - 31 23 16 - vss s ground 32 24 17 16 vdd s digital power supply 33 25 - - pb12 i/o ft spi1_nss (2) , spi2_nss (3) , tim1_bkin, eventout - table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions http:/// pinouts and pin descriptions stm32f030x4 stm32f030x6 stm32f030x8 28/89 docid024849 rev 1 34 26 - - pb13 i/o ft spi1_sck (2) , spi2_sck (3) , tim1_ch1n - 35 27 - - pb14 i/o ft spi1_miso (2) , spi2_miso (3) , tim1_ch2n, tim15_ch1 (3) - 36 28 - - pb15 i/o ft spi1_mosi (2) , spi2_mosi (3) , tim1_ch3n, tim15_ch1n (3) , tim15_ch2 (3) rtc_refin 37 - - - pc6 i/o ft tim3_ch1 - 38 - - - pc7 i/o ft tim3_ch2 - 39 - - - pc8 i/o ft tim3_ch3 - 40 - - - pc9 i/o ft tim3_ch4 - 41 29 18 - pa8 i/o ft usart1_ck, tim1_ch1, eventout, mco - 42 30 19 17 pa9 i/o ft usart1_tx, tim1_ch2, tim15_bkin (3) i2c1_scl (2) - 43 31 20 18 pa10 i/o ft usart1_rx, tim1_ch3, tim17_bkin i2c1_sda (2) - 44 32 21 - pa11 i/o ft usart1_cts, tim1_ch4, eventout - 45 33 22 - pa12 i/o ft usart1_rts, tim1_etr, eventout - 46 34 23 19 pa13 (swdio) i/o ft (5) ir_out, swdio - 47 35 - - pf6 i/o ft i2c1_scl (2) , i2c2_scl (3) - table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions http:/// docid024849 rev 1 29/89 stm32f030x4 stm32f030x6 stm32f030x8 pinouts and pin descriptions 32 48 36 - - pf7 i/o ft i2c1_sda (2) , i2c2_sda (3) - 49 37 24 20 pa14 (swclk) i/o ft (5) usart1_tx (2) , usart2_tx (3) , swclk - 50 38 25 - pa15 i/o ft spi1_nss, usart1_rx (2) , usart2_rx (3) , eventout - 51 - - - pc10 i/o ft - - 52--- pc11 i/oft - - 53 - - - pc12 i/o ft - - 54 - - - pd2 i/o ft tim3_etr - 55 39 26 - pb3 i/o ft spi1_sck, eventout - 56 40 27 - pb4 i/o ft spi1_miso, tim3_ch1, eventout - 57 41 28 - pb5 i/o ft spi1_mosi, i2c1_smba, tim16_bkin, tim3_ch2 - 58 42 29 - pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n - 59 43 30 - pb7 i/o ftf i2c1_sda, usart1_rx, tim17_ch1n - 60 44 31 1 boot0 i b boot memory selection 61 45 - - pb8 i/o ftf (5) i2c1_scl, tim16_ch1 - 62 46 - - pb9 i/o ftf i2c1_sda, ir_out, tim17_ch1, eventout - table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions http:/// pinouts and pin descriptions stm32f030x4 stm32f030x6 stm32f030x8 30/89 docid024849 rev 1 63 47 32 15 vss s ground 64 48 1 16 vdd s digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these gpios must not be used as current sources (e.g. to drive an led). 2. this feature is available on stm 32f030x6 and stm32f030x4 devices only. 3. this feature is available on stm32f030x8 devices only. 4. on lqfp32 package, pb2 and pb8 should be treate d as unconnected pins (even when they are not available on the package, they are not forced to a defined level by hardware). 5. after reset, these pins are configured as swdio and sw clk alternate functions, and the internal pull-up on swdio pin and internal pull-down on swclk pin are activated. table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 lqfp32 tssop20 alternate functions a dditional functions http:/// pinouts and pin descriptions stm32f030x4 stm32f030x6 stm32f030x8 31/89 docid024849 rev 1 table 12. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 pa0 - usart1_cts (1) 1. this feature is available on stm32f030x6 and stm32f030x4 devices only. ----- usart2_cts (2) 2. this feature is available on stm32f030x8 devices only. pa1 eventout usart1_rts (1) ----- usart2_rts (2) pa2 tim15_ch1 (2) usart1_tx (1) ----- usart2_tx (2) pa3 tim15_ch2 (2) usart1_rx (1) ----- usart2_rx (2) pa4 spi1_nss usart1_ck (1) - - tim14_ch1 - - usart2_ck (2) pa5 spi1_sck - - - - - - pa6 spi1_miso tim3_ch1 tim1_bkin - - tim16_ch1 eventout pa7 spi1_mosi tim3_ch2 tim1_ch1 n - tim14_ch1 tim17_ch1 eventout pa8 mco usart1_ck tim1_ch1 eventout - - - pa9 tim15_bkin (2) usart1_tx tim1_ch2 - i2c1_scl (1) -- pa10 tim17_bkin usart1_rx tim1_ch3 - i2c1_sda (1) -- pa11 eventout usart1_cts tim1_ch4 - - - - pa12 eventout usart1_rts tim1_etr - - - - pa13 swdio ir_out - - - - - pa14 swclk usart1_tx (1) ----- usart2_tx (2) pa15 spi1_nss usart1_rx (1) - eventout - - - usart2_rx (2) http:/// pinouts and pin descriptions stm32f030x4 stm32f030x6 stm32f030x8 32/89 docid024849 rev 1 table 13. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 pb0 eventout tim3_ch3 tim1_ch2n - pb1 tim14_ch1 tim3_ch4 tim1_ch3n - pb2 - - - - pb3 spi1_sck eventout - - pb4 spi1_miso tim3_ch1 eventout - pb5 spi1_mosi tim3_ch2 tim16_bkin i2c1_smba pb6 usart1_tx i2c1_scl tim16_ch1n - pb7 usart1_rx i2c1_sda tim17_ch1n - pb8 - i2c1_scl tim16_ch1 - pb9 ir_out i2c1_sda tim17_ch1 eventout pb10 - i2c1_scl (1) 1. this feature is available on stm32f030x6 and stm32f030x4 devices only. -- i2c2_scl (2) 2. this feature is available on stm32f030x8 devices only. pb11 eventout i2c1_sda (1) -- i2c2_sda (2) pb12 spi1_nss (1) eventout tim1_bkin - spi2_nss (2) pb13 spi1_sck (1) - tim1_ch1n - spi2_sck (2) pb14 spi1_miso (1) tim15_ch1 (2) tim1_ch2n - spi2_miso (2) pb15 spi1_mosi (1) tim15_ch2 (2) tim1_ch3n tim15_ch1n (2) spi2_mosi (2) http:/// docid024849 rev 1 33/89 stm32f030x4 stm32f030x6 stm32f030x8 memory mapping 35 5 memory mapping figure 7. stm32f030x memory map reserved ahb2 0 1 2 3 4 5 6 7 0xffff ffff peripherals sram flash memory reserved reserved system memory option bytes cortex- m internal peripherals 0xe010 0000 ms19840v1 ' m b t i t z t u f n n f n p s z p s 4 3 " . e f q f o e j o h p o # 0 0 5 d p o g j h v s b u j p o 0x0000 0000 0xe000 0000 0xc000 0000 0xa000 0000 0x8000 0000 0x6000 0000 0x4000 0000 0x2000 0000 0x0000 0000 y 0x0801 0000 0x1fff ec00 0x1fff f800 0x1fff fc00 0x1fff ffff 0x0001 0000 reserved code " 1 # " 1 # reserved 0x4000 0000 0x4000 8000 0x4001 0000 0x4001 8000 reserved 0x4002 0000 " ) # 0x4800 0000 reserved 0x4800 17ff 0x4002 43ff http:/// memory mapping stm32f030x4 stm32f030x6 stm32f030x8 34/89 docid024849 rev 1 table 14. stm32f030x peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 1000 - 0x4800 13ff 1 kb reserved 0x4800 0c00 - 0x4800 0fff 1 kb gpiod 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 3400 - 0x4002 43ff 4 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash interface 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0400 - 0x4002 0fff 3 kb reserved 0x4002 0000 - 0x4002 03ff 1 kb dma 0x4001 8000 - 0x4001 ffff 32 kb reserved apb 0x4001 5c00 - 0x4001 7fff 9 kb reserved 0x4001 5800 - 0x4001 5bff 1 kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 (1) 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb reserved 0x4001 2400 - 0x4001 27ff 1 kb adc 0x4001 0800 - 0x4001 23ff 7 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0000 - 0x4 001 03ff 1 kb syscfg 0x4000 8000 - 0x4000 ffff 32 kb reserved http:/// docid024849 rev 1 35/89 stm32f030x4 stm32f030x6 stm32f030x8 memory mapping 35 apb 0x4000 7400 - 0x4000 7fff 3 kb reserved 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 5c00 - 0x4000 6fff 5 kb reserved 0x4000 5800 - 0x4000 5bff 1 kb i2c2 (1) 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 4800 - 0x4000 53ff 3 kb reserved 0x4000 4400 - 0x4000 47ff 1 kb usart2 (1) 0x4000 3c00 - 0x4000 43ff 2 kb reserved 0x4000 3800 - 0x4000 3bff 1 kb spi2 (1) 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1 kb reserved 0x4000 2000 - 0x4000 23ff 1 kb tim14 0x4000 1400 - 0x4000 1fff 3 kb reserved 0x4000 1000 - 0x4000 13ff 1 kb tim6 (1) 0x4000 0800 - 0x4000 0fff 2 kb reserved 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb reserved 1. this feature is available on stm32f030x8 devices only. for stm32f030x6 and stm32f060x4, the area is reserved. table 14. stm32f030x peripheral register boundary addresses (continued) bus boundary address size peripheral http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 36/89 docid024849 rev 1 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading conditions figure 9. pin input voltage ms19210v1 c = 50 pf mcu pin ms19211v1 mcu pin v in http:/// docid024849 rev 1 37/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 6.1.6 power supply scheme figure 10. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. ms32141v1 an alo g: rcs, pll, ... gp i/o s out in kernel logic (cpu, digital & memories) lse, rtc, wake-up logic 2 100 nf + 1 4.7 f regulator v dda v ssa adc level shifter io logic v dd 10 nf + 1 f v dda v ref+ v ref- v dd v ss 2 2 http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 38/89 docid024849 rev 1 6.1.7 current consumption measurement figure 11. current consumption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 15: voltage characteristics , table 16: current characteristics , and table 17: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. ms32142v1 v dd v dda i dd i dda table 15. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) ?0.3 4.0 v v dd ?v dda allowed voltage difference for v dd >v dda -0.4v v in (2) 2. v in maximum must always be respected. refer to table 16: current characteristics for the maximum allowed inje cted current values. input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 v input voltage on tta pins v ss ? 0.3 4.0 v input voltage on any other pin v ss ?? 0.3 4.0 v | ? v ddx | variations between different v dd power pins - 50 mv |v ssx ?? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics http:/// docid024849 rev 1 39/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 table 16. current characteristics symbol ratings max. unit ? i vdd total current into sum of all vdd_x and vddsdx power lines (source) (1) 120 ma ? i vss total current out of sum of all vss_x and vsssd ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd_x or vddsdx power pin (source) (1) 100 i vss(pin) maximum current out of each vss_x or vsssd ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 ? i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 i inj(pin) injected current on ft, ftf and b pins (3) -5/+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 ? i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and gr ound (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between tw o consecutive power supply pins referring to high pin count qfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in >v dd while a negative injection is induced by v in docid024849 rev 1 41/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 6.3.2 operating conditions at power-up / power-down the parameters given in table 19 are derived from tests performed under the ambient temperature condition summarized in table 18 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 20 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18: general operating conditions . 6.3.4 embedded reference voltage the parameters given in table 21 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18: general operating conditions . table 19. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate 0 ? v dda fall time rate 20 ? table 20. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in t he option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 2.06 v rising edge 1.84 1.92 2.10 v v pdrhyst (1) pdr hysteresis - 40 - mv t rsttempo (3) 3. guaranteed by design, not tested in production. reset temporization 1.5 2.5 4.5 ms table 21. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +85 c 1.16 1.2 1.24 (1) v t s_vrefint (2) adc sampling time when reading the internal reference voltage - 5.1 17.1 (3) s http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 42/89 docid024849 rev 1 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 11: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz and 1 wait state above 24 mhz) ? prefetch is on when the peripherals are enabled, otherwise it is off (to enable prefetch the prftbe bit in the flash_acr re gister must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk = f hclk the parameters given in table 22 to are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . ? v refint internal reference voltage spread over the temperature range v dda = 3 v 10 mv - - 10 (3) mv t coeff temperature coefficient - - 100 (3) ppm/c 1. data based on characterization results, not tested in production. 2. shortest sampling time can be determined in the application by multiple iterations. 3. guaranteed by design, not tested in production. table 21. embedded internal reference voltage (continued) symbol parameter conditions min typ max unit http:/// docid024849 rev 1 43/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 table 22. typical and maximum current consumption from v dd supply at v dd = 3.6 symbol parameter conditions f hclk all peripherals enabled unit typ max @ t a (1) 1. data based on characterization results, not tested in production unless otherwise specified. 85 c i dd supply current in run mode, code executing from flash hsi clock, pll on 48 mhz 22 22.8 ma 24 mhz 12.2 13.2 hsi clock, pll off 8 mhz 4.4 5.2 supply current in run mode, code executing from ram hsi clock, pll on 48 mhz 22.2 23.2 24 mhz 11.2 12.2 hsi clock, pll off 8 mhz 4.0 4.5 supply current in sleep mode, code executing from flash or ram hsi clock, pll on 48 mhz 14 15.3 24 mhz 7.3 7.8 hsi clock, pll off 8 mhz 2.6 2.9 table 23. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) 1. current consumption from the v dda supply is independent of whether the peripherals are on or off. furthermore when the pll is off, i dda is independent from the frequency. f hclk v dda = 3.6 v unit typ max @ t a (2) 85 c 2. data based on characterization results, not tested in production. i dda supply current in run mode, code executing from flash or ram hse bypass, pll on 48 mhz 175 215 a hse bypass, pll off 8 mhz 3.9 4.9 1 mhz 3.9 4.1 hsi clock, pll on 48 mhz 244 275 hsi clock, pll off 8 mhz 85 105 supply current in sleep mode, code executing from flash or ram hse bypass, pll on 48 mhz 174 215 hse bypass, pll off 8 mhz 3.9 4.9 1 mhz 3.9 4.9 hsi clock, pll on 48 mhz 244 299 hsi clock, pll off 8 mhz 85 105 http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 44/89 docid024849 rev 1 table 24. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda ) max (1) 1. data based on characterization results, not tested in production unless otherwise specified. unit 3.6 v t a = 85 c i dd supply current in stop mode regulator in run mode, all oscillators off 19 48 a regulator in low-power mode, all oscillators off 532 supply current in standby mode lsi on and iwdg on 2 - table 25. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ @v dd (v dd = v dda ) max (1) 1. data based on characterization results, not tested in production. unit 3.6 v t a = 85 c i dda supply current in stop mode v dda monitoring on regulator in run or low power mode, all oscillators off 2.9 3.5 a supply current in standby mode lsi on and iwdg on 3.3 - lsi off and iwdg off 2.8 3.5 supply current in stop mode v dda monitoring off regulator in run mode or low power, all oscillators off 1.7 - supply current in standby mode lsi on and iwdg on 2.3 - lsi off and iwdg off 1.4 - http:/// docid024849 rev 1 45/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 typical current consumption the mcu is placed under the following conditions: ? v dd =v dda =3.3 v ? all i/o pins are in analog input configuration ? the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state above) ? prefetch is on when the peripherals are enabled, otherwise it is off ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively ? a development tool is connected to the board and the parasitic pull-up current is around 30 a table 26. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 23.3 11.5 ma 8 mhz 4.5 3.0 i dda supply current in run mode from v dda supply 48 mhz 158 158 a 8 mhz 2.43 2.43 http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 46/89 docid024849 rev 1 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 44: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 26: typical current consumption in r un mode, code with data processing running from flash ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c ? ? = http:/// docid024849 rev 1 47/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 6.3.6 wakeup time from low-power mode the wakeup times given in table 28 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the event used to wake up the device depends from the current o perating mode: ? stop or sleep mode: the wakeup event is wfe. ? the wakeup pin used in stop and sleep mode is pa0 and in standby mode is pa1. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18: general operating conditions . table 27. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value) i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 ma 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v dd = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 table 28. low-power mode wakeup timings symbol parameter conditions typ @v dd = 3.3 v max unit t wustop wakeup from stop mode regulator in run mode 4.2 5 s t wustandby wakeup from standby mode 50.96 - t wusleep wakeup from sleep mode 1.1 - http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 48/89 docid024849 rev 1 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 12: high-speed external clock source ac timing diagram . figure 12. high-speed external clock source ac timing diagram table 29. high-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f hse_ext user external clock source frequency 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 ms19214v2 v hseh t f(hse) 90% 10% t hse t t r(hse) v hsel t w(hseh) t w(hsel) http:/// docid024849 rev 1 49/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switch ed off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 13 . figure 13. low-speed external clock source ac timing diagram table 30. low-speed external user clock characteristics symbol parameter (1) 1. guaranteed by design, not tested in production. conditions min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 ms19215v2 v lseh t f(lse) 90% 10% t lse t t r(lse) v lsel t w(lseh) t w(lsel) http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 50/89 docid024849 rev 1 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 31 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high- frequency applications, and selected to match the requirements of the crystal or resonator (see figure 14 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 31. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by t he crystal/ceramic re sonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 - k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time -8.5 ma v dd =3.3 v, rm= 45 ? , cl=10 pf@8 mhz -0.5- v dd =3.3 v, rm= 30 ? , cl=20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this val ue is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms http:/// docid024849 rev 1 51/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 figure 14. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information gi ven in this paragraph are based on design simulation results obtained with typical external components specified in table 32 . in the application, the resonator and the load capa citors have to be placed as cl ose as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ms19876v1 osc_ou t osc_in f hse c l1 r f 8 mh z resonator r ext (1) c l2 resonator with integrated capacitors bias controlled gain table 32. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.5- a lsedrv[1:0]= 01 medium low driving capability -0.8- lsedrv[1:0] = 10 medium high driving capability -1.1- lsedrv[1:0]=11 higher driving capability -1.4- g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]= 01 medium low driving capability 8- - lsedrv[1:0] = 10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 52/89 docid024849 rev 1 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. figure 15. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. ms30253v1 osc32_ou t osc32_in f lse c l1 32.768 kh z resonator c l2 resonator with integrated capacitors drive programmable amplifier http:/// docid024849 rev 1 53/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 6.3.8 internal clock source characteristics the parameters given in table 33 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) table 33. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 85 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) (3) 3. with user calibration. t a = ?40 to 85 c - 5 - % t a = 25 c - 1 - % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption -80-a table 34. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 85 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - 14 mhz trim hsi14 user-trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 85 c - 5 - % t su(hsi14) hsi14 oscillator startup time 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption -100-a http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 54/89 docid024849 rev 1 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 36 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 18: general operating conditions . 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 85 c unless otherwise specified. table 35. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 85 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 - a table 36. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier fact ors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) -24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -48mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps table 37. flash memory characteristics symbol parameter co nditions min typ max (1) unit t prog 16-bit programming time t a ??? ?40 to +85 c - 53.5 - s t erase page (1 kb) erase time t a ?? ?40 to +85 c - 30 - ms t me mass erase time t a ?? ?40 to +85 c - 30 - ms i dd supply current write mode - - 10 ma erase mode - - 12 ma v prog programming voltage 2.4 - 3.6 v http:/// docid024849 rev 1 55/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 39 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. 1. guaranteed by design, not tested in production. table 38. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = ?40 to +85 c (6 suffix versions) 1 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 20 years table 39. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp64, t a ?? +25 c, f hclk ?? 48 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp64, t a ?? +25 c, f hclk ?? 48 mhz conforms to iec 61000-4-4 3b http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 56/89 docid024849 rev 1 software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 40. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd ?? 3.6 v, t a ?? 25 c, lqfp64 package compliant with iec 61967-2 0.1 to 30 mhz -3 dbv 30 to 130 mhz 28 130 mhz to 1ghz 23 sae emi level 4 - http:/// docid024849 rev 1 57/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (more than 5 lsb tue), out of conventional limits of current injection on adjacent pins (more than ?5 a) or other functional failu re (reset occurrence or osc illator frequency deviation, for example). the characterization results are given in table 43 . table 41. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to jesd22-c101 ii 500 table 42. electri cal sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 58/89 docid024849 rev 1 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 44 are derived from tests performed under the conditions summarized in table 18: general operating conditions . all i/os are designed as cmos and ttl compliant. table 43. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 ?0 na ma injected current on all ft and ftf pins with induced leakage current on adjacent pins less than ?5 a ?5 na injected current on all tta pins with induced leakage current on adjacent pins less than ?5 a ?5 +5 injected current on all tc and reset pins with induced leakage current on adjacent pins less than ?5 a ?5 +5 table 44. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v dd +0.07 (1) v ft and ftf i/o - - 0.475 v dd ?0.2 (1) boot0 - - 0.3 v dd ?0.3 (1) all i/os except boot0 pin - - 0.3 v dd v ih high level input voltage tc and tta i/o 0.445 v dd +0.398 (1) -- v ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 pin 0.7 v dd -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - http:/// docid024849 rev 1 59/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 16 for standard i/os, and in figure 17 for 5 v tolerant i/os. i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss ? v in ? v dd -- ? 0.1 a tta in digital mode v dd ? v in ? v dda -- 1 tta in analog mode v ss ? v in ? v dda -- ? 0.2 ft and ftf i/o (3) v dd ? v in ? 5v --10 r pu weak pull-up equivalent resistor (4) v in ?? v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (4) v in ?? v dd 25 40 55 k ? c io i/o pin capacitance -5 -pf 1. data based on design simulation only. not tested in production. 2. leakage could be higher than maximum value, if negat ive current is injected on adjacent pins. refer to table 43: i/o current injection susceptibility . 3. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. 4. pull-up and pull-down resistors are designed with a true resistance in series with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order). table 44. i/o static characteristics (continued) symbol parameter conditions min typ max unit http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 60/89 docid024849 rev 1 figure 16. tc and tta i/o input characteristics figure 17. five volt tolerant (ft and ftf) i/o input characteristics 0 0.5 1 1.5 2 2.5 3 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 cmos standard requirements v ihmin = 0.7 v dd v ihmin = 0.445 v dd + 0.398 tested range undefined input range v ilmax = 0.3 v dd + 0.07 v ilmax = 0.3 v dd cmos standard requirements tested range ttl standard requirement ttl standard requirement ms32130v1 v (v) in v (v) dd ms32131v1 0 0.5 1 1.5 2 2.5 3 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ttl standard requirement ttl standard requirement cmos standard requirements tested range v ihmin = 0.7 v dd v ihmin = 0.5 v dd + 0.2 v ilmax = 0.475 v dd - 0.2 undefined input range cmos standard requirements v ilmax = 0.3 v dd tested range v (v) dd v (v) in http:/// docid024849 rev 1 61/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 output driving current the gpios (general purpose input/outputs) can si nk or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see table 16: current characteristics ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating ? i vss (see table 16: current characteristics ). output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 18: general operating conditions . all i/os are cmos and ttl compliant (ft, tta or tc unless otherwise specified). table 45. output voltage characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 - v ol (1)(3) output low level voltage for an i/o pin when 5 pins are sunk at the same time i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v v oh (2)(3) output high level voltage for an i/o pin when 5 pins are sourced at the same time v dd ?1.3 - v ol (1)(3) output low level voltage for an i/o pin when 8 pins are sunk at the same time i io = +6 ma 2.4 v < v dd < 2.7 v -0.4 v v oh (2)(3) output high level voltage for an i/o pin when 8 pins are sourced at the same time v dd ?0.4 - v olfm+ (1) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma - 0.4 v 1. the i io current sunk by the device must always resp ect the absolute maximum rating specified in table 16: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vss . 2. the i io current sourced by the device must always res pect the absolute maximum rating specified in table 16: current characteristics and the sum of i io (i/o ports and control pins) must not exceed i vdd . 3. data based on characterization results. not tested in production. http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 62/89 docid024849 rev 1 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 18 and table 46 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 18: general operating conditions . table 46. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.4 v to 3.6 v - 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2.4 v to 3.6 v -125 (3) ns t r(io)out output low to high level rise time -125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.4 v to 3.6 v - 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2.4 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 c l = 50 pf, v dd = 2.4 v to 2.7 v - 20 t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2.4 v to 3.6 v - 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2.4 v to 3.6 v - 12 (3) ns t r(io)out output low to high level rise time c l = 50 pf, v dd = 2.4 v to 3.6 v - 34 (3) t extipw pulse width of external signals detected by the exti controller 10 - ns 1. the i/o speed is configured usin g the ospeedrx[1:0] bits. refer to the rm0091 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 18 . 3. guaranteed by design, not tested in production. 4. when fm+ configuration is set, the i/o speed cont rol is bypassed. refer to the stm32f0xx reference manual rm0091 for a detailed description of fm+ i/o configuration. http:/// docid024849 rev 1 63/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 figure 18. i/o ac charac teristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu (see table 44: i/o static characteristics ). unless otherwise specified, th e parameters given in the table below are derived from tests performed under ambient temperature and vdd supply voltage conditions summarized in table 18: general operating conditions . ms32132v1 t 10% 50% 90% 10% 50% 90% external output on 50 pf maximum frequency is achieved if (t + t ( 2/3)t and if the duty cycle is (45-55%) when loaded by 50 pf r f r(io)out t f(io)out t table 47. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage ?0.3 - 0.8 (1) v v ih(nrst) nrst input high level voltage 2-v dd +0.3 (1) v hys(nrst) nrst schmitt trigger voltage hysteresis -200-mv r pu weak pull-up equivalent resistor (2) v in ?? v ss 30 40 50 k ? v f(nrst) nrst input filtered pulse - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 300 (1) --ns 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 64/89 docid024849 rev 1 figure 19. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 47: nrst pin characteristics . otherwise the reset will not be taken into account by the device. ms19878v1 r pu nrst (2) v dd filter internal reset 0.1 f external reset circuit (1) http:/// docid024849 rev 1 65/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 48 are preliminary values derived from tests performed under ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in table 18: general operating conditions . note: it is recommended to perform a calibration after each power-up. table 48. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on 2.4 - 3.6 v f adc adc clock frequency 0.6 - 14 mhz f s (1) sampling rate 0.05 - 1 mhz f trig (1) external trigger frequency f adc = 14 mhz - - 823 khz --171/f adc v ain conversion voltage range 0 - v dda v r ain (1) external input impedance see equation 1 and table 49 for details --50k ? r adc (1) sampling switch resistance - - 1 k ? c adc (1) internal sample and hold capacitor --8pf t cal (1) calibration time f adc = 14 mhz 5.9 s 83 1/f adc t latr (1) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (1) sampling time f adc = 14 mhz 0.107 - 17.1 s 1.5 - 239.5 1/f adc t stab (1) power-up time 0 0 1 s t conv (1) total conversion time (including sampling time) f adc = 14 mhz 1 - 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. guaranteed by design, not tested in production. http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 66/89 docid024849 rev 1 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rmine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 49. r ain max for f adc = 14 mhz t s (cycles) t s (s) r ain max (k ? ) (1) 1. guaranteed by design, not tested in production. 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 50. adc accuracy (1)(2)(3) 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative inject ion current: injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. symbol parameter test conditions typ max (4) 4. data based on characterization results, not tested in production. unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? , v dda = 2.7 v to 3.6 v t a = ? 40 to 85 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 r ain t s f adc c adc 2 n2 + ?? ln ? ? ------------------------------------------------------------- - r adc ? ? http:/// docid024849 rev 1 67/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 figure 20. adc accuracy characteristics figure 21. typical connecti on diagram using the adc 1. refer to table 48: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 10: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ms19880v1 1lsb ideal 4096 v dda ms19881v2 v dda ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc 12-bit converter c adc sample and hold adc converter http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 68/89 docid024849 rev 1 6.3.17 temperature sensor characteristics 6.3.18 timer characteristics the parameters given in table 52 are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 51. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - ? 1 ? 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 - - s table 52. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim3, tim6, ti m14, tim15, tim16 and tim17 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1- t timxclk f timxclk = 48 mhz 20.8 - ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 48 mhz 0 24 mhz res tim timer resolution timx - 16 bit t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 48 mhz 0.0208 1365 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 48 mhz - 89.48 s http:/// docid024849 rev 1 69/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 table 53. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller?s internal rc frequency can vary from 30 to 60 khz. moreover, given an ex act rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 table 54. wwdg min-max ti meout value @48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 70/89 docid024849 rev 1 6.3.19 communication interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 55 . refer also to section 6.3.14: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . table 55. i2c characteristics (1) symbol parameter standard fast mode fast mode + unit min max min max min max f scl scl clock frequency 0 100 0 400 0 1000 khz t low low period of the scl clock 4.7 - 1.3 - 0.5 - s t high high period of the scl clock 4 0.6 0.26 - s tr rise time of both sda and scl signals - 1000 - 300 - 120 ns tf fall time of both sda and scl signals - 300 - 300 - 120 ns t hd;dat data hold time 0 - 0 - 0 - s t vd;dat data valid time - 3.45 (2) -0.9 (2) -0.45 (2) s t vd;ack data valid acknowledge time - 3.45 (2) -0.9 (2) -0.45 (2) s t su;dat data setup time 250 - 100 - 50 - ns t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - s t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - s c b capacitive load for each bus line - 400 - 400 - 550 pf 1. the i2c characteristics are the requirements from the i2c bus specification rev03. they are guaranteed by design whenthe i2cx_timing register is correctly programmed (refer to reference manual). these characteristics are not tested in production. 2. the maximum t hd;dat could be 3.45 s, 0.9 s and 0.45 s for standard mode, fast mode and fast mode plus, but must be less than the maximum of t vd;dat or t vd;ack by a transition time. http:/// docid024849 rev 1 71/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 figure 22. i 2 c bus ac waveforms and measurement circuit legend: rs : series protection resistors. rp: pull-up resistors. v dd_i2c : i 2 c bus supply. spi characteristics unless otherwise specified, the parameters given in table 57 are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 18: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristic s (nss, sck, mosi, miso for spi and ws, ck). table 56. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t sp pulse width of spikes that are suppressed by the analog filter 50 260 ns ms19879v3 rs i 2 c bus rp rs v dd_i2c mcu sda scl rp v dd_i2c m s 1 98 7 9 v 3 scl http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 72/89 docid024849 rev 1 table 57. spi characteristics symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) (1) nss setup time slave mode 4tpclk - ns t h(nss) (1) nss hold time slave mode 2tpclk + 10 - t w(sckh) (1) t w(sckl) (1) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) (1) t su(si) (1) data input setup time master mode 4 - slave mode 5 - t h(mi) (1) data input hold time master mode 4 - t h(si) (1) slave mode 5 - t a(so) (1)(2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (1)(3) data output disable time slave mode 0 18 t v(so) (1) data output valid time slave mode (after enable edge) - 22.5 t v(mo) (1) data output valid time master mode (after enable edge) - 6 t h(so) (1) data output hold time slave mode (after enable edge) 11.5 - t h(mo) (1) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output an d the max time is for the ma ximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z http:/// docid024849 rev 1 73/89 stm32f030x4 stm32f030x6 stm32f030x8 electrical characteristics 74 figure 23. spi timing diagram - slave mode and cpha = 0 figure 24. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input http:/// electrical characteristics stm32f030x4 stm32f030x6 stm32f030x8 74/89 docid024849 rev 1 figure 25. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck output cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck output cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo) http:/// docid024849 rev 1 75/89 stm32f030x4 stm32f030x6 stm32f030x8 package characteristics 86 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. http:/// package characteristics stm32f030x4 stm32f030x6 stm32f030x8 76/89 docid024849 rev 1 figure 26. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 table 58. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d. 7.500 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 03.57 03.57 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. http:/// docid024849 rev 1 77/89 stm32f030x4 stm32f030x6 stm32f030x8 package characteristics 86 figure 27. lqfp64 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 http:/// package characteristics stm32f030x4 stm32f030x6 stm32f030x8 78/89 docid024849 rev 1 figure 28. lqfp48 ? 7 x 7 mm, 48 pin low-profile quad flat package outline 1. drawing is not to scale. 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 table 59. lqfp48 ? 7 x 7 mm, 48-pin low- profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0. 0531 0.0551 0.0571 b 0.170 0.220 0.270 0. 0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0. 3465 0.3543 0.3622 d1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0. 3465 0.3543 0.3622 e1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0. 0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. http:/// docid024849 rev 1 79/89 stm32f030x4 stm32f030x6 stm32f030x8 package characteristics 86 figure 29. lqfp48 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 http:/// package characteristics stm32f030x4 stm32f030x6 stm32f030x8 80/89 docid024849 rev 1 figure 30. lqfp32 ? 7 x 7mm 32-pin low-profile quad flat package outline 1. drawing is not to scale. 5v_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 16 17 24 25 b 32 1 pin 1 identification 8 9 table 60. lqfp32 ? 7 x 7mm 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 5.600 0.2205 e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 5.600 0.2205 e 0.800 0.0315 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 1.000 0.0394 k 0.0 3.5 7.0 0.0 3.5 7.0 ccc 0.100 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. http:/// docid024849 rev 1 81/89 stm32f030x4 stm32f030x6 stm32f030x8 package characteristics 86 figure 31. lqfp32 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. 9.40 7.70 0.80 0.54 9.40 5v_fp http:/// package characteristics stm32f030x4 stm32f030x6 stm32f030x8 82/89 docid024849 rev 1 figure 32. tssop20 - 20-pin thin shrink small outline 1. drawing is not to scale. ya_me 1 20 cp c l e e1 d a2 a k e b 10 11 a1 l1 aaa table 61. tssop20 ? 20-pin thin shrink small outline package mechanical data symbol millimeters inches (1) min typ max min typ a 1.2 0.0472 a1 0.05 0.15 0.002 0.0059 a2 0.8 1 1.05 0.0315 0.0394 0.0413 b 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 d 6.4 6.5 6.6 0.252 0.2559 0.2598 e 6.2 6.4 6.6 0.2441 0.252 0.2598 e1 4.3 4.4 4.5 0.1693 0.1732 0.1772 e 0.65 0.0256 l 0.45 0.6 0.75 0.0177 0.0236 0.0295 l1 1 0.0394 k 0.0 8.0 0.0 8.0 aaa 0.1 0.0039 1. values in inches are converted from mm and rounded to 4 decimal digits. http:/// docid024849 rev 1 83/89 stm32f030x4 stm32f030x6 stm32f030x8 package characteristics 86 figure 33. tssop20 recommended footprint 1. dimensions are in millimeters http:/// package characteristics stm32f030x4 stm32f030x6 stm32f030x8 84/89 docid024849 rev 1 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 18: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: ? t a max is the maximum ambient temperature in c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org 7.2.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the stm32f0 xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature ra nge will be best suited to the application. the following examples show how to calculat e the temperature range needed for a given application. table 62. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp48 - 7 7 mm 55 thermal resistance junction-ambient lqfp32 - 7 7 mm 56 thermal resistance junction-ambient tssop20 110 http:/// docid024849 rev 1 85/89 stm32f030x4 stm32f030x6 stm32f030x8 package characteristics 86 example 1: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 62 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.115 c = 102.115 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c) see table 18: general operating conditions . in this case, parts must be ordered at leas t with the temperature range suffix 6 (see section 8: part numbering ). note: with this given p dmax we can find the t amax allowed for a given device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (45c/w 447 mw) = 105-20.115 = 84.885 c suffix 7: t amax = t jmax - (45c/w 447 mw) = 125-20.115 = 104.885 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following ap plication conditions: maximum ambient temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 62 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 100 c + (45 c/w 134 mw) = 100 c + 6.03 c = 106.03 c this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. http:/// package characteristics stm32f030x4 stm32f030x6 stm32f030x8 86/89 docid024849 rev 1 refer to figure 34 to select the required temperature range (suffix 6 or 7) according to your ambient temperature or power requirements. for suffix 7, refer to stm32f05x devices. figure 34. lqfp64 p d max vs. t a msv32143v1 600 0 100 200 300 400 500 700 65 75 85 95 105 115 125 135 suffix 6 suffix 7 p d (mw) t a (c) http:/// docid024849 rev 1 87/89 stm32f030x4 stm32f030x6 stm32f030x8 part numbering 87 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please cont act your nearest st sales office. table 63. ordering information scheme example : stm32 f 030 r 8 t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 030 = stm32f030xx pin count f = 20 pins k = 32 pins c = 48 pins r = 64 pins code size 4 = 16 kbytes of flash memory 6 = 32 kbytes of flash memory 8 = 64 kbytes of flash memory package p = tssop t = lqfp temperature range 6 = ?40 c to +85 c options tr = tape and real http:/// revision history stm32f030x4 stm32f030x6 stm32f030x8 88/89 docid024849 rev 1 9 revision history table 64. document revision history date revision changes 03-jul-2013 1 initial release http:/// docid024849 rev 1 89/89 stm32f030x4 stm32f030x6 stm32f030x8 89 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com http:/// |
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